When an electronic system is switched on, an external power supply voltage (VDDE) is supplied to various component integrated circuit semiconductor devices, and ramps up during a certain tRAMP time interval. The status of a digital semiconductor device is generally preset or initialized during power on once the supply voltage of the integrated circuits in the device has reached a correct level. This is done to start operations correctly at the end of the power on phase.
A power on reset (POR) generator integrated in the device is used for initialization during power on. The generated POR signal is high until VDDE reaches a predetermined level (VPOR+), which is required for the initialization during power on. Thereafter, the POR signal switches to low and the semiconductor device operates in a stand-by mode.
FIG. 1 shows a simplified functional block diagram of a semiconductor device, which includes an on-chip voltage down converter (VDC). A description of each block follows.
PORE_GEN: is an external power on reset signal generator that generates the PORE signal during external power supply (VDDE) ramp up. The externally generated PORE signal has the function of resetting the REF_GEN and the VDC blocks.
REF_GEN: generates a compensated stable reference voltage (VREF_VDC) that is used in an on-chip voltage down converter VDC.
VDC: is an on-chip voltage down converter that converts VDDE to a stable regulated internal voltage supply (VDDI) using VREF_VDC for regulating it.
PORI_GEN: is an internal power on reset generator that generates the internal signal PORI when a stable regulated internal voltage supply VDDI is produced by the VDC block. The PORI signal is used for resetting and initializing core parts of the IC.
The core parts of the semiconductor device use the stable regulated internal supply voltage VDDI produced by the on-chip VDC. Typically, there is a large capacitance between VDDI and GND.
FIG. 2 shows a simplified PORE dynamics when VDDE is powered up and powered down with a ramping time tRAMP. During VDDE ramp up, POR follows VDDE, and POR is in a High state until VDDE reaches a predetermined level (VPOR_TH+: POR threshold voltage during power up); a POR High keeps the device in a reset condition. During VDDE ramp down, POR switches to a High state when VDDE is lower than VPOR_TH− (POR threshold voltage during power down). The difference between VPOR_TH+ and VPOR_TH− ensures a hysteresis for filtering out the noise in the power supply voltage during the power up period.
FIG. 3 shows a simplified PORI dynamics when VDDE is ramping up and down with a tRAMP time, and VDDI is being generated by VDC when converting the external supplying voltage VDDE. Due to this conversion, the VDC response time induces a time lag between VDDE and VDDI during power up and down. During power down of VDDE and VDDI there is an additional time lag due to the capacitive load (Cpara) between VDDI that needs time to be discharged, and GND. It may be observed that the relationship between PORI and VDDI is almost the same as that of PORE and VDDE.
FIG. 4 shows a basic circuit diagram used for both the first or primary power on reset circuit PORE_GEN, and for the second or secondary power on reset circuit PORI_GEN. The two circuits are identical and function with VDD equal to the external VDDE and VDDI, respectively. The circuit includes three parts, and the details of each part are explained as follows.
Part1 is a nonlinear voltage divider composed of a PMOS active resistor and a P+ diffusion passive resistor. The PMOS active resistor enhances the response time when the power up ramping time is fast. The P+ passive resistor formed on an NWELL ensures a stable resistance value with respect to process spread, and prevents possible ground bouncing during internal operations. An active P+ diffusion resistor introduces a parasitic capacitance between the P+ diffusion and VDD.
Part2 is an inverter-type level detector. The POR signal switches to low when VREF_POR reaches the logic threshold of the inverter made of PMOS0, NMOS0 and NMOS1. A feedback network connected to PMOS1, PMOS2 and NMOS2 provide for a certain hysteresis of the POR threshold voltage during power up and power down.
Part3 is an optional fuse for selecting a PMOS active resistor value in the Part1 current implemented to provide a choice between different external power supply voltage ratings of the device, such as for either a 1.8V or a 3.0V supply voltage. For example, considering the PORE_GEN, when VDD starts rising, the VREF_POR voltage evolves as a voltage ratio of the input supply voltage VDDE. When VREF_POR reaches the threshold voltage of the level detector, the NODE_F flips and the PORE signal switches to a low state for driving the device to a stand-by mode. During the stand-by mode, there is a static DC current flowing in the POR circuit according to the equation I=VREF_POR/(Resistance of P+ diffusion resistor).
FIG. 5 shows the simulation results for different tRAMPs with VDD=3.0V and a resistance of P+0.25 Mohm. With a relatively short tRMAP (fast power up//power down), the POR signal is generated at a higher (/lower) voltage than VPOR+min (/VPOR-max) because the parasitic capacitance on VREF_POR increases its precharge (/discharge) time through the PMOS (/P+) resistor. With a relatively long tRAMP (slow power up//power down), the POR signal is generated almost coincidently with the VPOR+min (/VPOR-max).
The drawbacks of known POR circuits as the one described above may be summarized as follows. First, the known circuits are unable to work reliably when the time interval between power down and power up becomes very short.
FIG. 6 shows the relationships among signals: VDDE, VDDI, PORE and PORI. When the time interval between power down and power up is short (re: dotted circle A), VDDI can not follow up VDDE because VDDI needs time to discharge the capacitive load (Cpara of FIG. 1). Therefore, the PORI does not operate correctly as it becomes unable to detect a VDDE glitch.
Secondly, the known circuits have an unwanted coupling effect caused by parasitic capacitance when the P+ resistance value is increased for reducing stand-by current absorption.
FIGS. 7 and 8 show simulation results of the POR threshold voltage versus power up or power down times (tRAMP) with resistance values of 0.5 Mohm and 1.0 Mohm, respectively, in order to assess the consequential behavior of the POR threshold voltage. FIG. 7 shows a certain lowering of the POR+ threshold voltage upon increasing the P+ resistance. Such a phenomenon can be explained by an increase of the parasitic capacitance between the enlarged P+ diffusion resistor and the supply node VDD. Of course, there are parasitic capacitances of NODE_F with respect to VDD and GND.
FIG. 8 shows the POR threshold voltage behavior as a presence of a parasitic capacitance between the inverter output node NODE_F of FIG. 4 and GND.
On another account, minimizing or reducing static DC current absorption during a stand-by mode in a POR circuit by increasing the passive resistance portion of the input supply voltage divider is a general requirement of digital devices.
Several approaches to reduce the stand-by current have been attempted. However, these attempts were unsuccessful because of following drawbacks. A first approach is replacing the P+ resistor with an N+ resistor, and increasing the resistance. With this approach, a very good POR threshold dynamics is achieved during power up, but is unsatisfactory during power down because the N+ resistor is formed on a P-substrate biased to GND. Therefore, there is a large parasitic capacitance between N+ resistor and GND.
A second approach is replacing the P+ resistor with a poly resistor and increasing the resistance. With this approach, the POR threshold dynamics is very good during power up, but again unsatisfactory during power down due to the large parasitic capacitance between the poly resistor and GND. Moreover, the resistance of the poly resistor is subject to large process variations, which results in a large spread of VPOR+.
A third approach is the use of a large P+ resistor and the addition of a compensating capacitor between VREF_POR and GND. With this approach, the POR threshold dynamics is very good during power up, but unsatisfactory during power down due to the time of discharge to GND through the P+ resistor.